[simpits-tech] MCC838 - Obscure decade counter chip

[Alan Murray]

Hello Alex,

A proper truth table in the Motorola documentation
would really help. Specifically the Q4(not) ties back
to the second gate input. When your reset drives that
high, the 2nd gate (essentially a NOR) correctly
drives Q2 and subsequently Q3 low which gives you the
output you are getting...

What does the counter do without the NAND gate in the
circuit? Same thing right? It is a decade counter, so
it seems to be set up in a divide-by-5 and a
divide-by-2. Think of it as the counter is counting to
5 and then setting the MSB high (Q4) and then it
counts to 5 again and sets it back to 0. That is what
it should be doing. If it does, you will not need your
NAND gate if it rolls over on five by itself.

Try it and let us know...and try putting your truth
table in this order Q4 Q3 Q2 Q1 instead of the other
way around...;)

Alan

--- alex <alex at flyinglow.ca> wrote:

> I'm trying to build a binary clock with some surplus
> digital logic chips I have laying around. The chip
> of choice it seems would be the 7490, of which I
> have 1 that works properly and 1 that seems to only
> work if I leave it in the default mode of counting
> from 0 to 9. I also have a number of chips stamped
> with MCC838, which turns out to be a decade counter
> like the 7490.
> 
> The main exception is the 838 has 4 inputs to
> explicitly set the bits with and a single reset
> line. I need to configure 3 counters to reset after
> reaching 5 (on 6 reset to 0). With the 7490, just
> tie the second bit to one reset and the third bit to
> the other reset and assuming the chip works, it
> counts 0, 1, 2, 3, 4, 5, 0, ....
> 
> Studying the spec sheet
> (http://www.datasheetarchive.com/pdf/2291586.pdf)  I
> could find on the MC838 leads me to believe that by
> using a NAND gate on bits 2 & 3 the result should
> nicely drive the CD (reset?) line from High-to-Low
> and hence reset the counter back to 0. However, that
> is not what is happening. Hear is the observed
> output:
> 
> 1 2 4 8 NAND
> 0 0 0 0 1
> 1 0 0 0 1
> 0 1 0 0 1
> 1 1 0 0 1
> 0 0 1 0 1
> 1 0 1 0 1 
> 
>  - at this point, the next clock should create 0110
> (6) and the NAND goes low (0) which should reset the
> 838 counter and start over. However, the counter
> just skips 6 & 7 and carries on with 8 as follows...
> 
> 0 0 0 1 1
> 1 0 0 1 1
> 0 0 0 0 1
> 
> Any ideas?
> 
> Alex
> http://www.flyinglow.ca
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